The USB Interface module was developed to be used with the Burched FPGA development board. It was developed for use in house to allow easy acces to registers in designs we’re developing, but may be marketed as a means of increasing hits to this web site.
You can download a .zip file of a basic demonstration application here. This contains the entire C++ Builder4 project, but if the USB drivers are installed as explained in the (included) SW_README file, the application should run stand alone.
The project’s vhdl files, a *.ucf and a FPGA_README file which explains in detail how to build the demo with Xilinx’s Webpack can be downloaded here.

The example above is a very simple example and is fairly inefficient, the PC wastes a lot of time waiting to receive characters from the USB board. Contact us for details of a much more efficient version.
Email us (details on the contact page) if you might be interested in buying an interface board. If there’s enough interest we’ll organise a small production run.

This Perl testbench generator automatically generates testbenches from VHDL design files. This script is well commented as to how it can be used. It’s basic with only some error checking, but it helps with the drudgery of testbench generation. (This had to be zipped to stop the server trying to run it when it’s selected, it’s only 9K long).

The Fast Open utility discussed on the Perl page can be downloaded. There are two different versions, one for Win9X and one for Win2K. The Win2K version should also work on NT. The code is commented with instructions for use and is a good demonstration of the flexibility of Perl with the Tk graphical extension.
The Picoblaze is a small free Xilinx CPU core. Download a quick start tutorial to get a very simple project running on a BurchED B5-X300 board here
A discussion on converting the VirtexII version of the Picoblaze (with 1024 instruction addresses instead of just 256) to run on a SpartanII device can be found here. The example project mentioned can be downloaded here