Aurora 64b66b Interface IP

Product Overview

The Aurora 64B/66B Interop IP Core is a high-performance FPGA-to-FPGA serial communication solution implementing Aurora-compatible 64B/66B framing over a single high-speed transceiver lane.

The core enables seamless interoperability between Efinix® FPGA devices and AMD/Xilinx® FPGA devices, as well as native Efinix-to-Efinix connectivity, operating at line rates up to 10Gbps.

Designed for deterministic behavior and rapid hardware bring-up, the architecture integrates cleanly into modern FPGA systems using a standard AXI-4 streaming (framed) user interface.

Key Features

• Aurora 64B/66B compatible framing and block alignment
• Single-lane serial architecture
• Line rate support up to 10Gbps (device dependent)
• AXI-4 user interface for system-level integration
• Reference design(s) for rapid evaluation and bring-up
• Optional RTL delivery for customization and long-term maintainability

Device Compatibility

Efinix

• Supported families: Titanium, Topaz (device dependent)

AMD/Xilinx

• Compatible with Aurora 64B/66B endpoints implemented on GTX, GTH, or GTY transceivers (device dependent)

Altera/ Intel

• An Altera version of the IP will be developed soon, initially targeting the Arria 10GX

Final device and tool support is defined per target FPGA family and project configuration.

Integration

The IP Core is delivered with supporting material to accelerate system integration and validation:

• Reference design(s)
• Integration and bring-up user guide guide

Deliverables

Available delivery options:

• Encrypted time-limited release for full evaluation.
• Encrypted source release (commercial license)
• Full RTL source code package with testbench (commercial RTL license)